In general, the high clock frequencies of modern integrated circuits (ICs) typically result in the supply current changing at speeds exceeding the ability of typical off-chip power supplies. As a result, on-chip power supply decoupling capacitance structures are typically provided to more quickly respond to changing power supply requirements demanded by the IC. With ICs generally operating at higher speeds, lower voltages and higher current levels, the demand for on-chip decoupling capacitance (decap) structures has generally increased, requiring a higher capacitance per unit area on the IC.
Many IC's are now designed using cell libraries. That is, the IC can be designed using circuit elements laid out in individual cells having at least one fixed dimension, such as a fixed height. The cells are then typically placed in a plurality of rows and interconnected by metal interconnect structures of the IC to provide the desired functionality. Such cell libraries typically include cells for many types of circuit elements, including decap cells. These decap cells are generally placed after the other portions of the integrated circuit are placed. Therefore, typical cell-based layouts include decap cells filling as much as possible of the remaining empty portions of the IC remaining after placement of the cells and interconnect structures providing the IC's functionality in order to provide as much capacitance as possible. Consequently, a large fraction of the typical cell-based IC is generally filled with decap cells, with the remaining unused space generally filled with conventional testing filler cells.
In metal-insulator-semiconductor (MIS) designs, decap cells generally comprise transistors having their gate connected to one power supply line (e.g. Vss or ground) and the source/drain and body connected to one other power supply line (e.g. Vdd). The capacitance provided in such decap cells is based on the area of the gate electrode over active area. These transistors generally have a thicker gate dielectric, referred to herein as TGOX (e.g., that of high voltage transistors, such as I/O transistors) than that of other standard cells in the IC, referred to herein as THINOX (having logic gates or memory) to minimize leakage current through the gate dielectric. For example, in a typical IC process using silicon dioxide comprising gate dielectrics, the thickness of the gate oxide used for the decap gate dielectric is generally about double or triple the thickness of gate oxide for standard transistor comprising cells.
The mask layout of a typical standard cell-based decap filler cell 100 is shown in FIG. 1. Nwell 114, cell border region 112, and PMOS transistors 102a and 102b within Nwell 114. Cell border 112 is shown. As well known in the art, although not corresponding to a particular physical structure, cell border 112 is a boundary between two adjacent standard cells that would be recognizable by one having ordinary skill in the art, such as the midpoint between the periphery device portions of two adjacent cells.
PMOS transistors 102a and 102b include gate electrodes 110a and 110b and associated P+ diffusion layer 106. Diffusion/active layer 106 is coupled to Vdd by layer 117 over contacts 104a, 104b, 104c, while gate electrodes 110a and 110b are coupled to Vss by layer 118 over gate contacts 105a and 105b. Regions outside diffusion/active layer 106 including border region are inactive, generally thick dielectric regions, such as comprising shallow trench isolation (STI) oxide.
A shown in FIG. 1, a decap gate dielectric mask 108 generally surrounds the transistors 102a, 102b in the layout of decap cell 100. The mask edge of decap gate dielectric 108 generally requires sufficient overlap shown as “ds” to the mask edge of the active portion of gate electrodes 110a, 110b (defined by diffusion/active layer 106), and sufficient spacing shown as “de” to the cell border 112 so that cell 100 has adequate spacing to any device that can appear in an adjacent cell, such as thin dielectric based standard cells (e.g. including logic devices or memory devices). Although only 2 transistor-based capacitor structures 102a and 102b are shown in the decap cell 100, and both are PMOS, any number of transistors can be used in the layout, NMOS based decaps can be used, and in one embodiment the decap cell can include both PMOS and NMOS-based decaps.
In decap cells, efficiency is generally defined as the fraction of the cell area which provides capacitance. It is generally desirable for the decap cells in an IC design to have as high efficiency as possible. The efficiency in a typical decap cell, such as cell 100, is generally influenced by three factors. First, when the cell is large in the x dimension, multiple transistors 102a, 102b are laid out to avoid the long time constants associated with a single large transistor. Although, such a design requires additional decap cell area to be spent for the additional source/drain contacts 104a, 104b, 104c required in the layout and represents lost efficiency, this lost efficiency being generally minor in view of other effects. Second, there is usually a density limit on the diffusion/active layer 106. In particular, the diffusion/active layer 106 cannot generally occupy more than a certain percentage of the area in large regions, depending on the process technology. This limitation results in reduced decap cell efficiency that is generally difficult to recover by optimizing the amount of area designed for the diffusion/active layer 106.
The final efficiency reducing factor results from the required decap gate dielectric mask overlap (ds) and spacing to the cell edge (de) described above. The decap gate dielectric mask 108 being spaced a significant distance within border 112 of the cell 100 results in the active edge of gate electrode mask being a large distance within the border region 112 of the cell 100, limiting cell capacitance and this cell efficiency.
Design rules require large overlap (ds) and spacing (de) because conventional standard cell layout techniques assume that each standard cell in a cell-based design is a single, separate entity and can be any available device. Furthermore, it is generally desirable to keep mask costs are low for forming the decap cell 100 by using large feature sizes and spacing, in particular for the decap gate dielectric mask 108. Therefore, conventional layout methodologies and the design rules for decap filler cells continue to generally do not utilize large areas around the periphery of the cell 100 for capacitance.
For example, as shown in FIG. 2, the decap gate dielectric mask which defines TGOX regions 208, 210, and 216, in decap cells 202, 204, and 214, respectively, is shown placed adjacent to a standard cell 206 that includes THINOX region 212 defined by a THINOX mask. A single transistor 219 is shown associated with THINOX region 212, although standard cell 206 generally includes a plurality of logic or memory devices. Design rules require the THINOX mask edge defining region 212 to be at least a minimum distance from the thick dielectric mask edge in cells 202, 210 and 214 shown as min dTHINOX. In a MOS-based design using both TGOX and THINOX layers, the TGOX design rules result in a minimum TGOX to TGOX spacing between the TGOX 208 mask edge in the bottom row and TGOX 210 mask edge in the upper row (shown as dTGOX in FIG. 2 which is 2 times ‘de’ shown in FIG. 1). Similarly, the design rules generally provide a minimum TGOX to THINOX mask edge spacing (dTHINOX) between the TGOX mask portions 208, 210 and THINOX mask region 212 in standard cell 206.
Furthermore, the loss in efficiency generally worsens as design rules for other layers are further scaled without scaling design rules decap gate dielectrics. Therefore, what is needed is a standard cell-based methodology and resulting integrated circuits which improve the efficiency for decap filler cells.